Direct memory access (DMA) controllers allow hardware subsystems within a computing system to access memory with limited effort from a central microprocessor unit. To illustrate general DMA functionality, consider the example of FIG. 1A, which illustrates a digital system 100 including a microprocessor 102, memory 104, DMA controller 106, and input/output block 108; all of which are operably coupled via a system bus 110. Without the DMA controller 106, successive read and write operations associated with a large data transfer, for example copying data within memory 104 or moving data to or from I/O block 108, can fully occupy the microprocessor 102 for an extended time period. With the DMA controller 106 in place, however, the microprocessor 102 provides some minimal programming for the DMA controller 106 and, after programming the DMA controller 106, the microprocessor 102 can go about other tasks while the DMA controller handles the data transfer.
More particularly, to transfer data, DMA controller 106 can make use of linked list structure 150, which is stored in memory 104, as shown in FIG. 1B. This linked list structure 150 includes multiple links 152 (e.g., DMA Link 1, DMA Link 2, . . . , DMA Link N), where each link includes a data field 154 and a reference field 156. The data field 154 points to data to be transferred for the corresponding link, and the reference field 156 points to the next link in the linked list structure 150. In the example of FIGS. 1A-1B, the microprocessor 102 programs the DMA controller 106 with the first link (DMA Link 1), and the DMA controller 106 subsequently transfers data as specified in the data field 154 of DMA Link 1. The DMA controller 106 then identifies the location of the second link (DMA Link 2) from reference field 156 of the first link, retrieves the second link (DMA Link 2) from memory 104, and transfers data as specified in data field of DMA Link 2. The DMA controller 106 then moves onto the third DMA Link, fourth DMA link, and so on. After all links in the linked list 150 have been processed (i.e., and the full data transfer completed), the DMA controller 106 can flag an interrupt (IRQ) to notify the microprocessor 102 that the data transfer is complete.
Although this conventional linked-list DMA technique allows the microprocessor 102 to offload some computational effort to the DMA controller 106 for large data transfers, these techniques still require ongoing “hold-holding” or management by the microprocessor 102 for the DMA controller 106 for many applications. Aspects of the present disclosure provide DMA controllers that exhibit greater independence from microprocessors, and thus, potentially enhanced system performance.